this post was submitted on 08 Feb 2025
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RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

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China's SpacemiT develops "VitalStone V100" 64-core RISC-V datacenter CPU on 12nm (www.tomshardware.com)
submitted 2 weeks ago* (last edited 2 weeks ago) by cypherpunks@lemmy.ml to c/riscv@lemmy.ml
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[–] merthyr1831@lemmy.ml 4 points 2 weeks ago

Do we have cores beyond the performance of the c910 yet? Im hoping to see RISCV get to ARM A72+ this year